Location: IIT Kharagpur

Modern chips consist of 100s of cores varying in size and complexity. After manufacturing of the chip, all cores need to be tested under various constraints as fast as possible. This problem is amplified further in 3D ICs. In this work, we explore if evolutionary algorithms such as Particle Swarm Optimization can be used to schedule testing the cores in parallel and minimize test time without violating constraints. We show an improvement of 51% over the SOTA.

Papers : M.Tech Dissertation, ATS 2015, VTS 2015, VDAT 2014 / Skills : C++, Digital Circuits